1. Field of the Invention
The present invention relates to a PLL circuit. More particularly, it relates to a PLL circuit which can improve spurious output characteristics.
2. Description of the Related Art
[Description of Prior Art: FIG. 7]
A typical phase locked loop (PLL) circuit will be described with reference to FIG. 7. FIG. 7 is a constitution block diagram showing a constitution of the typical PLL circuit.
As shown in FIG. 7, the typical PLL circuit is constituted of a voltage-controlled oscillator (VCO) 1, a PLL IC 2, a direct digital synthesizer (DDS) circuit 4′ and an analog filter 5.
The VCO 1 oscillates a frequency in accordance with a control voltage from the analog filter 5.
The PLL IC 2 is an integrated circuit which divides the output frequency of the VCO 1 at a set frequency division ratio and which compares the frequency with a reference frequency from the DDS circuit 4′, thereby outputting a voltage to control the output frequency of the VCO 1 so that the frequency becomes a regulated frequency, and the circuit is made of one chip.
The DDS circuit 4′ generates and outputs a reference frequency signal based on a set channel number.
The analog filter 5 extracts a direct-current component from the voltage from the PLL IC 2 to output the control voltage of the VCO 1.
In the PLL circuit having the above constitution, the PLL IC 2 divides the output signal of the VCO 1 input into the PLL IC at a designated frequency division ratio, compares the phase of the signal with that of the reference frequency signal from the DDS circuit 4′ to output the voltage based on a phase difference, and the direct-current component is extracted through the analog filter 5 to obtain and apply the control voltage to the VCO 1. In consequence, an output Fout of the VCO 1 has a regulated frequency.
[DDS Circuit 4′: FIG. 8]
Here, a schematic constitution of the DDS circuit 4′ in the conventional PLL circuit will be described with reference to FIG. 8. FIG. 8 is a schematic constitution diagram of the conventional DDS circuit 4′.
As shown in FIG. 8, the basic constitution of the conventional DDS circuit 4′ comprises a control section 41′ and a reference frequency table 43.
In the reference frequency table 43, the reference frequencies corresponding to the channel numbers are stored.
Moreover, upon input of the channel number, the control section 41′ reads the reference frequency with reference to the reference frequency table 43 to output corresponding sine wave data.
Furthermore, a D/A converter (not shown) converts a signal into an analog signal, and the signal is output as a reference frequency signal to the PLL IC 2 through a filter.
[Deterioration Due to Spurious Output: FIG. 9]
When the above PLL circuit is used as a synthesizer, the reference frequency from the DDS circuit 4′ or the setting of the frequency division ratio of the PLL IC 2 can be varied to obtain a plurality of channel outputs.
However, as to some of channels, the reference frequency from the DDS circuit 4′ or the output of the PLL IC 2 includes a spurious component, and eventually the spurious output of the VCO 1 is generated sometimes.
Moreover, this deterioration due to the spurious output has a dependency on temperature sometimes.
Here, the spurious output characteristics of the VCO 1 will be described with respect to channels 0 to 600 in a case where the frequency division ratio (div) of the PLL IC 2 is varied in the typical PLL circuit with respect to FIG. 9. FIG. 9 is a schematic explanatory view of the spurious output characteristics of the VCO 1 in the typical PLL circuit.
FIG. 9 shows the spurious output characteristics of the VCO 1 in a case where the frequency division ratio of the PLL IC 2 is changed to 133, 135 and 137. It is seen from FIG. 9 that even at any of the frequency division ratios, the channel is present in which the spurious output characteristics remarkably deteriorate. That is, each channel has the frequency division ratio at which the spurious output characteristics are satisfactory and the frequency division ratio at which the spurious output characteristics are not satisfactory, and the characteristics differ with the channels.
[Concerned Technologies]
Examples of a technology concerning the PLL circuit include Japanese Patent Application Laid-Open No. 2004-166179 titled “Semiconductor Integrated Circuit Device for Radio Communication” (applicant: NEC KANSAI LTD., Patent Document 1) and Japanese Patent Application Laid-Open No. 2003-69426 titled “Frequency Synthesizer” (applicant: Matsushita Electric IND. CO. LTD., Patent Document 2).
Moreover, examples of a technology concerning the frequency synthesizer include Japanese Patent Application Laid-Open No. 2007-208367 titled “Synchronizing Signal Generating Apparatus, Transmitter and Control Method” (applicant: KENWOOD CORP., Patent Document 3).
Patent Document 1 discloses a PLL circuit in which a channel number is set through a microcomputer to obtain the optimum frequency division number N or A, thereby alleviating a load on the microcomputer.
However, in Patent Document 1, a reference frequency fr has a fixed value, and it is not described that the frequency is variable.
Patent Document 2 discloses a frequency synthesizer in which even when a reference frequency signal fluctuates in accordance with a temperature change, a frequency division ratio is adjusted in accordance with the temperature change to decrease the fluctuation of an output frequency.
However, it is not described in Patent Document 2 that the reference frequency signal is intentionally fluctuated to suppress the deterioration due to the spurious output.
Patent Document 3 discloses that the frequency division ratio of a PLL circuit, the output frequency/input frequency of a DDS and the like are regulated so that the combination of the input signal frequency and output signal frequency of the DDS sets the spurious output of the DDS to a predetermined level or below.